1. Field of the Invention
The invention relates generally to high-speed integrated circuit output buffer circuits, and more particularly to a system and method for reducing the amount of ground bounce introduced by integrated circuit output buffer circuit operation.
2. Related Art
Integrated circuits are commonplace in contemporary electronic and computer-related equipment. Such equipment often comprises multiple integrated circuits interfaced to each other via data busses or other signal paths. Interface specifications for various logic families in use delineate voltage and current levels required for digital signals to be transferred between two or more integrated circuits.
To meet these interface specifications, integrated circuits use an output buffer circuit to drive a logic-low or logic-high signal across the signal path. Output buffer circuits are also used as a way of interfacing one logic type of an integrated circuit to a second logic type of a second integrated circuit.
Output buffer circuits use a voltage level, Vcc, as a source of the logic high level. Vcc is typically 3.0 to 5.5 volts (which is usually positive), depending on the technology used. The supply voltage for Vcc is typically introduced into the integrated circuit at an integrated circuit package pin. The integrated circuit package pin is connected to a pad on the microcircuit chip by a bond wire, so as to provide the Vcc to the microcircuit chip. The Vcc is distributed throughout the microcircuit on a (power) bus or other signal path as an internal Vcc supply.
Output buffer circuits use a system ground (GND) as a sink for a logic low output. GND is also introduced into the integrated circuit at an integrated circuit package pin and connected to a pad on the microcircuit chip by a bond wire. GND is distributed throughout the microcircuit chip on a (power) bus or other signal path.
Inherent in the bond wires and integrated circuit pins that interface to the microcircuit are a capacitance, resistance and inductance. These characteristics are affected by design selections such as wire and pin length, thickness, and materials.
Output buffer circuits typically use two field effect transistors (FETs) connected to an output terminal. A first FET is a p-channel pull-up transistor, whose source is connected to Vcc, and whose drain is connected to the output terminal.
A second FET is an n-channel pull-down transistor, whose drain is connected to the output terminal, and whose source is connected to ground.
An input data signal controls each FET at its gate via control logic. To output a logic high signal, the pull-up (first) FET is turned on by the control logic, and the pull-down (second) FET is turned off. Output switching to this high state allows current to flow from Vcc to the output terminal via the first FET, and puts the pull-down (second) FET in a high-impedance state so that no output signal current may flow through it to GND.
To output a logic low signal, pull-up (first) FET is turned off, thus presenting a high resistance between Vcc and the output terminal. In this low state, no current will flow from Vcc to the output terminal. Simultaneously, pull-down (second) FET is turned on, thus allowing current to pass from the output terminal to GND. As a result, the output buffer circuit acts as a sink for current, and the output signal is a logic low signal.
Thus, it can be seen that to transition the signal at the output terminal from one state to another state requires switching one of the FETs on while switching the other FET off.
As contemporary systems are advancing to offer greater performance in terms of speed, microcircuit technology has seen the emergence of sub-micron technology. Microcircuits using sub-micron technology inherently have much faster transition times than previous technologies due to the smaller channel length dimensions of the fabricated devices. Although faster transition times are beneficial for increasing circuit speed, faster transition times result in sudden surges of current in the course of changing state. Sudden surges in current result in what are commonly known as current spikes. Thus, rapid switching of the pull-up and pull-down FETs results in current spikes on the output during a time period immediately following a change of state.
Additionally, during output switching, charging and discharging currents are generated from the FETs to a load capacitance (C.sub.L) present at the output.
These currents (current spikes and charging and discharging currents), which appear during output switching, are known as transient currents. These transient currents are present on the Vcc and GND, and induce corresponding voltage transients (also called switching noise) on Vcc and GND.
The switching noise causes the integrity of the logic high and logic low states of the output buffer circuit to be degraded. This undesirable noise is commonly referred to as ground bounce. If severe enough, such degradation results in interface problems among the output buffer circuit and other ICs to which it interfaces. The interface problems occur when the degradation causes the logic low and logic high states of the output buffer circuit to be out of specification.
In most integrated circuits, the problem of ground bounce is compounded by simultaneous switching of multiple output buffer circuits. Most integrated circuits have such simultaneous switching because of the use of parallel bus structures. The direction of the technology is toward even wider parallel bus structures. Ground bounce becomes more severe as more output buffers switch simultaneously.